1. Field of the Invention
The present invention relates to data processing systems, and more particularly to an improved input/output processor for interfacing a number of peripheral subsystems employing different communication disciplines with a general-purpose data processor.
2. Description of the Prior Art
In copending patent application Ser. No. 971,661 of Stephen R. Colley et al, entitled "Data Processing System," filed Dec. 21, 1978, there is disclosed an object-oriented data processor architecture which takes full advantage of recent advances in the state-of-the-art of very large-scale, integrated circuit technology. An object-based access mechanism is employed by both the general-purpose data processors and the input/output processors within the system. An object is a representation of related information maintained in a contiguously addressed set of memory locations. Two basic types of objects are recognized and distinguished by a processor. The first basic type (a data segment) contains ordinary data such as characters, integers, reals, etc. The second basic type (an access list) contains access descriptors. Each access descriptor provides information for locating and defining the extent of access to an object associated with that access descriptor. Processors construct complex objects by combinations of objects of the basic types. Mechanisms within the processor identify the types of complex objects and control their use.
One such complex object, a context, defines an environment made up of objects accessible to a given instance of a procedural operation. Processors recognize context objects and utilize them in process execution.
Two other types of hardware-recognizable objects, buffered communication ports and dispatching ports, are defined to provide communication between processors, and the dispatching of ready-to-run processors for execution, respectively.
The generalized data processors (GDP) perform generalized computation over a wide spectrum of data types supported by this type of processor. The input/output processor (IOP) transfers data between two address spaces that it has access to and can reference. For example, transferring data from an input device which exists in the I/O address space, into a data segment which exists in the GDP address space.
An IOP uses the same descriptor controlled segment-based address development mechanism as the GDP. The I/O operations also execute in a context-based environment similar to that provided for the GDP. An IOP also uses the same interprocess communication mechanism and IOPs are selected for service via a dispatching mechanism similar to that used by GDPs.
Because an input/output processor must interface with a number of different types of peripheral subsystems in addition to interfacing with generalized data processors, and must handle asynchronous types of operations, the circuitry for such a processor is very complex. This complexity creates certain problems when implementing an input/output processor in large-scale integrated circuit technology. These limitations include limitations on the number of input/output pins which are available on integrated circuit chips and limitations as to the amount of circuitry which can be fabricated on a single chip with current technology. To overcome these limitations, it is desirable to provide an input/output interface which will allow a plurality of different types of existing microprocessors to be connected to and work with the new data processing architecture. With such an arrangement, input/output operations of the type described above can be performed by the external processor, thus reducing the complexity of the input/output processor requirements. There must be provided an interface by which an external processor can be connected to the system and address the main memory as well as function compatibly with the main system's object-oriented architecture. Such an interface must be able to recognize addresses generated by the external processor, and map these addresses onto the address space of main memory. Furthermore, such an interface must be able to allow the external processor to communicate with processes and processors of the main system. The following is a summary of some of the prior approaches to the problem of interfacing a peripheral subsystem to a data processing system.
In Moreton U.S. Pat. No. 4,035,777 a multiprocessing system is disclosed in which each functional unit produces a response signal when it detects its own address on the bus. A port unit is provided on each functional unit chip and stores each address applied to an internal bus to which it is connected. The port unit functions to apply the stored address to the main bus if no response signal is detected within a predetermined time period. Thus, the port unit does not have to be provided with any information about which addresses are on the main bus and which are on the internal bus as it assumes that all addresses which do not produce any response on the internal bus must correspond to the main bus. Thus, in this system, additional units can be added or removed without modifying the port unit.
Each of the functional units contain a plurality of blocks of storage space, and a storage allocation list which maintains a plurality of pointers identifying the blocks of storage. The list of pointers is then used to dynamically allocate storage space by inserting or removing pointers from the list.
This patent does not disclose means for mapping peripheral subsystem addresses onto the address space of main memory, nor does it provide a functional capability over system objects stored in main memory.
Hendrie et al U.S. Pat. No. 4,048,673 discloses an input/output controller (IOC) fabricated on a chip for communication between a CPU and peripheral devices. It includes a 15-bit address and block length registers for block-oriented peripheral data transfer operations. It does not disclose a structure for providing for mapping of addresses.
Bennett et al U.S. Pat. No. 4,069,510 discloses a peripheral interface adapter which is fabricated on a single chip. The patent addresses the problem of interfacing a processor to a variety of peripheral units having varying logical and electrical interfacing requirements. It uses a control register to allow restructuring of the logical functions under program control. This allows address expansion, and redefinition of peripheral interface pins. It does not, however, show the mapping peripheral of addresses into an address space in a common memory.
Davis et al U.S. Pat. No. 4,075,691 discloses a peripheral control unit which includes a small special-purpose programmable computer. A microcode enables this computer to handle the different communication disciplines corresponding to the various peripheral devices. The control unit includes a direct memory-access module (DMA) which generates the starting address in core memory and sends or receives the 16-bit data word. This patent does not disclose the concept of mapping IO addresses onto an address space in a common shared memory.
Larson Defensive Publication T940019 discloses a computer system in which a supervisory program translates input/output "virtual" addresses which are mapped into corresponding real addresses in memory. This publication does not show the concept of mapping a portion of the IO address space in a memory in order to support data transfer between two address spaces whereby data is transferred from IO devices to main memory or is transferred from main memory to IO devices.
It is therefore a primary object of the present invention to provide a new input/output Interface apparatus which is designed to efficiently utilize large-scale, integrated circuit technology.
It is a further object of this invention to provide an input/output architectural structure which supports an object-oriented data processing system architecture and enables compatibility with systems which do not employ that architecture.
It is also an object of this invention to provide a map facility for mapping an address range from the address space of an external processor into the address space of an object-oriented data processor.
It is also an object of this invention to provide apparatus whereby software running on an external processor is given a window into the address space of an object-oriented processor that enables the software, via the execution of a limited subset of main processor instructions, to send and receive messages from said main processor and to manipulate an environment provided for the external software within the main processor address space.